1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, in particular, to a multi-layered wiring structure including main power-supply lines, main ground (or grounding) lines, signal lines, and the like.
2. Description of the Related Art
Recently, in the technical field of semiconductor devices, DRAM/logic mixed LSIs have become the focus of attention. Each DRAM/logic mixed LSI provides DRAM functions and logic functions on a single chip. FIG. 9 is a diagram showing the structure of an example of the DRAM/logic mixed LSI. As shown in the figure, in the DRAM/logic mixed LSI. DRAM area 31 and logic circuit area 32 are provided on a single chip 30. In addition, a plurality of pads 33 are arranged in a peripheral area of the chip. FIG. 5 is a partially-enlarged view of the DRAM area 31.
In the following explanation, the xe2x80x9cmask blockxe2x80x9d corresponds to an area in which a circuit is formed, and a plurality of mask blocks form a xe2x80x9cmask block shelfxe2x80x9d. Additionally, in FIG. 5, each reference numeral in the brackets indicates a specific kind of wiring.
In FIG. 5, transistors, capacitors, and the like, arranged in lower layers, are not shown in the DRAM area 1, and only wiring lines are shown. In this area, a three-layered aluminum (Al) wiring structure is employed, which includes (i) first AL wiring lines 34 (see finely shaded lines) vertically arranged in FIG. 5, (ii) second AL wiring lines 35 horizontally arranged in FIG. 5, and (iii) third AL wiring lines 36 (see roughly shaded lines) horizontally arranged in FIG. 5. In the present specification, the first AL wiring lines indicate the AL wiring lines formed in the first layer from the bottom of the three-layered AL wiring structure, the second AL wiring lines indicate the AL wiring lines formed in the second layer from the bottom of the three-layered AL wiring structure, and the third AL wiring lines indicate the AL wiring lines formed in the third layer from the bottom of the three-layered AL wiring structure.
In the illustrated DRAM/logic mixed LSI, each first AL wiring line 34 is used as (i) a line for vertically connecting a P-channel transistor and an N-channel transistor in a mask block, (ii) a power-supply line (called a xe2x80x9cVDD linexe2x80x9d, hereinafter) 41 or a ground (or grounding or earth) line (called a xe2x80x9cGND linexe2x80x9d, hereinafter) 42 in a mask block, (iii) a signal line for connecting vertically adjacent mask block shelves, or the like.
Each second AL wiring line 35 is used as a VDD line 38 or a GND line 39 in a mask block shelf, a wide area signal line (called a xe2x80x9cbus linexe2x80x9d, hereinafter) 40, or the like.
Each third AL wiring line 36 is used as a main VDD line 43 or a main GND line 44 which has a larger width and which is used in common between mask block shelves, or the like. Generally, in conventional DRAMs, the main VDD lines, main GND lines, and the like are formed using the second AL wiring lines. However, in the no DRAM/logic mixed LSI, the above-explained structure is often employed as required by the design of relevant logic circuits.
FIG. 6 is an enlarged view of an area (see the circled area indicated by reference symbol D in FIG. 5) where the first AL wiring line 34, the second AL wiring line 35, and the third AL wiring line 36 are connected so as to provide a GND line arrangement. FIG. 7 is a cross-sectional view along line Bxe2x80x94B in FIG. 6. As shown in FIG. 6, enlarged portion 42a (enlarged in the width direction) is formed in the GND line 42 formed by the first AL wiring line 34, and first through holes 45 and second through holes 46, having the same diameter (or width), are formed in a manner such that they are vertically aligned. Between the first through holes 45 and the second through holes 46, a GND line 39 formed by the second AL wiring line 35 is provided, and a main GND line 44 formed by the third AL wiring line 36 is provided above the second through holes 46.
FIG. 7 is a cross-sectional view of the above area shown in FIG. 6, and FIG. 7 also shows a portion including a transistor. As shown in FIG. 7, transistor 50 is formed on silicon substrate 47, which comprises a gate electrode 48, and N+ diffusion layers 49a and 49b functioning as source and drain electrodes. The first AL wiring lines 34 formed on the first inter-layer insulating film 51 are respectively connected to N+ diffusion layers 49a and 49b via the first contacts 52. On one of the GND lines 42 formed by the first AL wiring line, the fist through holes 45, passing through the second inter-layer insulating film 53, are formed. The GND line 42 formed by the first AL wiring line 34 and the GND line 39 formed by the second AL wiring line 35 are connected via the first conductors 55 in the first through holes 45.
In addition, above the GND line 39 formed by the second AL wiring line 35, the second through holes 46 are formed, which pass through the third inter-layer insulating film 56. The GND line 39 formed by the second AL wiring line 35 and the main GND line 44 formed by the third AL wiring line 36 are connected via the second conductors 58 in the second through holes 46. Therefore, the earth voltage of the main GND line 44 formed by the third AL wiring line 36 is supplied via the GND line 39 formed by the second AL wiring line 35 to the GND line 42 formed by the first AL wiring line 34. Here, the arrangement including the VDD lines is not shown, but has a similar structure.
The conventional DRAM/logic mixed LSI having the above-explained structure has the following problems.
FIG. 7 shows the portion where the first, second, and third AL wiring lines are connected so as to provide a GND line arrangement, while FIG. 8 shows a sectional view (along line Exe2x80x94E in FIG. 6) showing a portion where the bus line 40 are provided. In the DRAM/logic mixed LSI, the bus line 40 is formed by the second AL wiring line 35, and the main GND line 44 is formed by the third AL wiring line 36. Therefore, as shown in FIG. 8, the main GND line 44 having a larger width is positioned above the bus line 40, while below the bus line 40, the first AL wiring line 34 is positioned. Accordingly, the bus line is positioned between the first and third AL wiring lines via each inter-layer insulating film; thus, capacity (or capacitance) is generated at either side of the bus line, thereby increasing the parasitic capacitance of the bus line.
Depending on the increase of the parasitic capacitance of the bus line, the delay of the signal passing through the relevant bus line is also increased, so that the timing between the above signal and the other signals becomes out of order, which may cause various kinds of operational errors. Therefore, in order to adjust the signal timing between a plurality of bus lines, lines for adjusting the wiring capacity are provided in advance, the mask pattern is changed according to need, and the line for adjusting the wiring capacity is connected to any bus line, so that the wiring capacity is adjusted between the bus lines. In the above DRAM/logic mixed LSI, such lines for adjusting the wiring capacity are formed in advance by using the second AL wiring line, that is, formed in the same layer as that of each bus line, and the formed lines function as AL master slice signal lines used for changing the pattern.
In the design and experimental manufacture of a device, it is important to quickly complete the debugging process of the characteristics of the product. However, in the above DRAM/logic mixed LSI, the AL master slice signal lines for changing the pattern are formed in the second layer of the three-layer wiring structure; thus, the mask pattern in the second AL wiring lines is changed, and after the relevant mask is formed, the manufacturing processes (carried out on the wafer) before the patterning of the second AL wiring lines are started again. Therefore, the time necessary for completing the processes from the change of the mask pattern to the completion of the product is relatively long, thereby causing a delay in the development of the device.
On the other hand, when the timing disorder between the signals of a plurality of bus lines is evaluated, or other various characteristics are evaluated, it is the simplest and quickest method to perform the characteristic measurement by bringing the probe of a tester into direct contact with the AL wiring line of the target bus line in the wafer. However, the main GND line having a larger width formed by the third AL wiring line is positioned above the second AL wiring line; thus, the main GND line is an obstacle, that makes the direct contact of the probe with the bus line impossible. In this case, a hole may be provided through the main GND line, insulating film, and the like positioned above the bus line, by using an FIB (focused ion beam) or the like, so as to probe the bus line. However, in this method, the time and labor necessary for evaluating the characteristics are very large.
In order to solve the above problems, an objective of the present invention is to provide a semiconductor device and a manufacturing method thereof, by which the parasitic capacitance of each signal line can be decreased and the time necessary for developing the device can also be decreased. Another objective of the present invention is to provide a semiconductor device having a structure by which the characteristic evaluation of the semiconductor device can be simply and quickly performed.
Therefore, the present invention provides a semiconductor device comprising:
a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and
an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer, wherein:
a window is formed in said one of the main power-supply line and the main ground line; and
the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.
Preferably, the upper-layer signal line is formed by the uppermost layer of a multi-layered structure.
In the conventional wiring-arrangement technique explained above, if (i) a signal line (i.e., bus line) is present in an intermediate layer of a multi-layered wiring structure, (ii) a main GND or VDD line having a wider width is positioned in an upper layer of the multi-layered wiring structure, and (iii) another signal line is positioned in a lower layer of the multi-layered wiring structure, the parasitic capacitance of the signal line of the intermediate layer is large because the signal line is positioned between the upper and lower wiring lines. In contrast, in the semiconductor device according to the present invention, the positional relationship between the main GND or VDD line and the upper-layer signal line is reversed in comparison with the conventional case. That is, in the semiconductor device of the present invention, the main GND or VDD line having a wider width is formed in an intermediate layer, and a relevant signal line is present at the upper side thereof. Therefore, as for this signal line, the capacitance is generated only at the lower side of the signal line, thereby decreasing the parasitic capacitance of the signal line in comparison with the conventional case.
Also in the structure according to the present invention, the main GND or VDD line having a wider width is not an obstacle for measuring the characteristics, that is, the characteristic measurement can be performed by bringing the probe of a tester into direct contact with the exposed upper-layer signal line before another film, such as a passivation film, is formed on the upper-layer signal line. Therefore, the process of opening a hole using an FIB or the like (which is necessary in the conventional case) is unnecessary. Accordingly, the time and labor necessary for measuring the characteristics of the device can be decreased.
In particular, if the upper-layer signal line is formed by the uppermost layer of a multi-layered structure, it is further preferable that a wiring line for adjusting the wiring capacity of the upper-layer signal line be formed by the same wiring layer as that for forming the upper-layer signal line, that is, by the uppermost layer. In this case, when the wiring capacitance of the signal line is adjusted, the target layer whose mask pattern must be modified is the uppermost wiring layer; thus, the necessary processes from the modification of the mask pattern to the completion of the relevant product are fewer. Therefore, time necessary for debugging of the characteristics of the product can also be shorter, thereby shortening the schedule for developing the device.
More specifically, it is possible that the lower-layer signal line is formed by the nth wiring layer, where n is a natural number of 1 or more; said one of the main power-supply line and the main ground line is formed by the (n+1)th wiring layer; and the upper-layer signal line is formed by the (n+2)th wiring layer. For example, the lower-layer signal line may be formed by the first AL (aluminum) wiring line, the main VDD or GND line may be formed by the second AL wiring line, and the upper-layer signal line may be formed by the third AL wiring line. However, the arrangement according to the present invention is not limited to the above structure if the positional relationship between each wiring line has the order (from the bottom side) of the lower-layer signal linexe2x86x92the main VDD or GND linexe2x86x92the upper-layer signal line.
As for the electric connection between the lower-layer signal line and the upper-layer signal line in the space inside the window, the lower-layer signal line formed by the first AL wiring line may be connected with the upper-layer signal line formed by the third AL wiring line via a through hole which passes through insulating films of different layers, but a process for realizing such a structure is very difficult. Therefore, in a preferable example of connecting these signal lines, a conducting portion is provided in a space inside the window in a manner such that the conducting portion is isolated from said one of the main power-supply line and the main ground line; and the lower-layer signal line and the conducting portion are connected via a through hole, and the conducting portion and the upper-layer signal line are connected via a through hole.
More preferably, a plurality of the through holes are provided at either side of the conducting portion. In this case, even if the contact state of one of the two through holes becomes defective, conduction between the upper-layer signal line and the lower-layer signal line does not become defective if the other through hole is normal. Therefore, the reliability of wiring and the yield on products can be improved.
In addition, the upper-layer signal line may be used as a wide area signal line (i.e., bus line).
The present invention also provides a method of manufacturing a semiconductor device, comprising the processes of:
forming a lower-layer signal line on a semiconductor substrate via a first insulating film;
forming a second insulating film with which the lower-layer signal line is covered;
forming a first through hole which passes through the second insulating film and reaches the lower-layer signal line;
embedding a first conductor in the first through hole;
forming one of a main power-supply line and a main ground line on the second insulating film, which has a window for providing a space above the first conductor, and
forming a conducting portion on the first conductor inside the window, where the conducting portion is isolated from said one of the main power-supply line and the main ground line;
forming a third insulating film with which the conducting portion and said one of the main power-supply line and the main ground line are covered;
forming a second through hole which passes through the third insulating film and reaches the conducting portion;
embedding a second conductor in the second through hole; and
forming an upper-layer signal line on the second conductor.
According to this method, the semiconductor device (of the present invention) having the above-explained effects can be manufactured without using a special manufacturing process. In addition, after the upper-layer signal line is formed, a characteristic measurement can be performed by bringing a probe of a tester into direct contact with the exposed upper-layer signal line.